ASIC Technical Program Manager

Title: ASIC Technical Program Manager

Reporting to: TBD

Location: Silicon Valley, CA



Avicena is seeking a Technical Program Manager (TPM) with significant ASIC/SoC design experience.  The ideal candidate will have a proven track record in managing complex semiconductor and packaging projects.  The role requires exceptional technical expertise, leadership, and organizational skills.  Familiarity with 3D chip stacking and/or optics is highly desired.  You will own programs central to the company success and revenue plans.

Key Responsibilities
  • Own complex multi-ASIC and integrated optics projects from conception through delivery.
  • Act as the primary point of contact for all program stakeholders, vendors, and customers; ensuring effective communication and alignment of expectations and schedules.
  • Manage all aspects of a program lifecycle. Including scope, schedule, resources, staffing, quality, costs, risks, and mitigations.
  • Work with internal and external stakeholders to plan projects down to the task level. This includes defining deliverables, duration, dependencies, and owners.
  • Work with customers and inbound marketing to create and evaluate product performance metrics. Diagnose, track, and resolve product issues.
  • Create and enforce process templates and industry standards for best-practice design, validation, bring-up, test, manufacturing, and communication channels; simultaneously keeping the individual contributor overhead as low as possible.
  • Generate automated project dashboards, task/bug tracking, and reporting systems.
  • Facilitate decision-making processes to drive progress and resolve conflicts.
  • Champion continuous improvement in processes.
  • Bachelor’s degree or higher in Electrical Engineering, Physics, or a related field.
  • 10+ years in engineering including 4+ years of experience as a technical program manager of ASIC products.
  • Demonstrated experience in the full life-cycle of SoC product development and manufacturing.
  • Strong technical knowledge of semiconductor design, fabrication, packaging, and testing.
  • Experience selecting and integrating external IP into ASIC designs.
  • Ability to collaborate with engineers, vendors, and customers; and report to executives.
  • Ability to easily converse with subject matter experts in SystemVerilog, UVM, high-speed design, electromagnetism, optics, mechanical and thermal engineering, semiconductor manufacturing, and advanced packaging.
  • Highly desirable to have experience with complex silicon packaging such as multi-chip modules, silicon interposers, TSVs, wafer/die bonding, 2.5D and 3D silicon stacking.
  • Highly desirable to have experience in optoelectronic components and optical packaging.
  • Highly desirable to have experience in high-speed PHYs and mixed-signal design.
  • Experience with DRAM is a plus.

About Avicena

Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (

To learn more about this position and career opportunities at Avicena, contact