Avicena will showcase its multi-Tbps LED-based optical link for chip-to-chip communication at ECOC 2021

Highly parallel optical links with power efficiency of 0.1pJ/bit, and bandwidth density of 10Tbps/mm2 promise to smash current interconnect bottlenecks in distributed compute systems

MOUNTAIN VIEW, CA and BORDEAUX, FRANCE — September 13, 2021 —

Avicena Tech Corp., a privately held company in Mountain View, CA, is demonstrating its LightBundleTM multi-Tbps LED-based chip-to-chip interconnect technology at the European Conference for Optical Communications (ECOC) 2021 in Bordeaux, France  (https://www.ecocexhibition.com/).

The Avicena LightBundleTM achieves order-of-magnitude improvements in power dissipation and density over any other interconnect technology up to a reach of 10 meters. LightBundleTM is purpose-built for multi-Tbps chip-to-chip interconnects in distributed computing, processor-to-memory disaggregation, and other advanced computing applications. LightBundleTM is based on arrays of novel GaN high-speed micro-emitters that leverage the microLED display manufacturing ecosystem and is fully compatible with high performance CMOS ICs.

“The cloud and high-performance computing market is looking for a new class of energy efficient high bandwidth density interconnects. Avicena’s technology has the potential to deliver a paradigm shift in terms of power efficiency, bandwidth density, and reach.”

Interconnects are becoming the key bottleneck in modern compute and network systems. Highly variable workloads are driving the evolution of densely interconnected, heterogeneous, software-defined clusters of CPUs, Graphical Processing Units (GPUs), Data Processing Units (DPUs) and shared memory blocks. Exploding Artificial Intelligence (AI) and Machine Learning (ML) workloads are exemplary of emerging applications driving an accelerating need for interconnects with extremely high density, low power consumption and low latency.

“The cloud and high-performance computing market is looking for a new class of energy efficient high bandwidth density interconnects,” said Vladimir Kozlov, Founder and CEO of LightCounting. “Avicena’s technology has the potential to deliver a paradigm shift in terms of power efficiency, bandwidth density, and reach.”

About the Technology

Today’s high-performance ICs use SerDes-based electrical links to achieve adequate IO density. However, the power consumption and bandwidth density of electrical links degrade quickly with length. Because optical interconnects have low attenuation, they have long been the prime contender to replace electrical interconnects for inter-chip communications. Unfortunately, conventional optical technologies (typically designed for networking applications) have been impractical for inter-processor and processor-memory interconnects due to their low bandwidth density, high-power consumption, and inability to tolerate the high operating temperature of ASICs.

“All of this is changing with the recent progress in optical emitter technology driven by advances in the display industry,” says Bardia Pezeshki, founder and CEO of Avicena. “We have developed super-efficient, high-density optical transmitters based on emitter technology from the display industry. These innovative devices would have been impractical just a few years ago. Our optimized devices and materials support 10Gbps links per lane over -40°C to +125°C temperature with excellent reliability. We refer to our new optical sources as Cavity-Reinforced Optical Micro-Emitters or CROMEs. We connect CROME arrays with CMOS compatible PDs using multi-core fiber bundles to create massively parallel interconnects with 100s of parallel lanes with a density of 10Tbps/mm2 over a reach of up to 10m. We call this new class of optical interconnect the Avicena LightBundleTM.”

Avicena’s CROMEs are about an order of magnitude faster than the current state-of-the-art LEDs. At 200 parallel lanes this extrapolates to an aggregate link bandwidth of 2Tbps with a bandwidth density of 10Tbps/mm2.

The parallel nature of the LightBundleTM technology is well matched to parallel chiplet interfaces like AIB, HBI, and BoW, and can also be used to extend the reach of standard compute interconnects like PCIe/CXL, NVLink, and multi-channel DDR/GDDR memory links with low power and low latency.

If you wish to learn more about the Avicena technology, here is a list of upcoming events:

Avicena at ECOC 2021
  • Market Focus, Mo. Sept 13, 1:55pm – 2:25pm CET, Chris Pfistner, “Novel LED based parallel optical interconnects with 10Tbps/mm2 @ < 0.5pJ/bit for chip-to-chip communication”
  • Technical Paper ID 0367, Session We1D VCSELs in Room D, Sept 15, 10.15 am, B. Pezeshki et al., “8x2Gb/s LED-Based Optical Link at 420nm for Chip-to-Chip Applications

Avicena cover story in the Special Edition of Compound Semiconductor Magazine for September 2021:

  • Compound Semiconductor, Special Edition, September 2021, Chris Pfistner, “How COVID-19 enabled a great invention at Avicena”
About Avicena

Avicena Tech Corp. is a privately held company located in Mountain View, CA, specializing in the development of next-generation chip-to-chip interconnects that are more power efficient, offer higher bandwidth density and support longer reach than any current optical or electrical solution. Avicena’s technology is a key building block in the evolution of new computer architectures that will reduce the energy impact on our planet.

Avicena Media Contact:
Sama Pourmojib
email: sama@avicena.tech

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